A 6–8-GHz Cryo-CMOS Fractional-N CP-PLL With Temperature Variation Calibration and Flicker Noise Suppression in 28-nm Bulk CMOS

This article presents a 6–8-GHz fractional-N charge-pump-phase-lock-loop (CP-PLL) working down to 3.5 K temperature in 28-nm bulk CMOS for quantum computing. To accommodate the wide operating temperature and frequency tuning ranges, a self-biased current source calibration method is introduced to maintain a constant charge pump bias current, thereby ensuring adequate phase margin and minimizing phase noise. An automatic flicker noise calibration technique is also employed to mitigate flicker noise degradation, while a sampled loop filter is utilized to reduce spur degradation at cryogenic temperatures. Owing to these methods, this phase-lock loop (PLL) achieves a phase noise of −90 dBc/Hz at 10 kHz and a jitter of 445 fs at cryogenic temperature while using a power consumption of 4.93 mW. The reference spur is below −70 dB although the mismatch of charge pump degrades at least$2\times $at cryogenic temperature.