Analytical Model for Gate-Induced Drain Leakage Current Degradation in Polycrystalline Silicon Thin-Film Transistors Under DC Drain Voltage Stress

An analytical degradation model for gate-induced drain leakage current ( I $_{\text{GIDL}}$ ) in polycrystalline silicon thin-film transistors (TFTs) under dc drain bias stress is proposed for the first time in this work. By analyzing the phenomenon of I $_{\text{GIDL}}$ degradation, the physical processes are systematically divided into four interrelated stages. Each stage's degradation parameters are modeled to develop a fixed charge model that accounts for stress time and stress voltage. Through deriving the corresponding expressions, the final degradation formula for I $_{\text{GIDL}}$ is obtained. Finally, the proposed model is validated through testing with varying stress time and stress voltages across different wafers.