Improvement of Endurance and Data-retention in 40nm TaO<inf>X</inf>-based ReRAM by Finalize Verify

This paper investigates Set/Reset endurance cycles utilizing Verify operation in order to extend the acceptable data-retention time of 40nm TaO _X based Resistive Random Access Memory (ReRAM). Applying Verify operation enhances data-retention time drastically at low Set/Reset cycles. However, as Set/Reset cycles with applying Verify operation increase, ReRAM-cell deteriorates and bit-error rate (BER) of low resistance state (LRS) increases [1]. To suppress this deterioration by Verify-stress, “Finalize_Verify” is proposed. As a result, the data-retention time of LRS is enhanced even at the high Set/Reset cycles. In addition, assuming to using error-correcting code (ECC), effect of ECC strength in Verify operation and Finalize_Verify operation is investigated.