计算机科学
瓶颈
带宽(计算)
探测器
信号处理
卷积神经网络
尖峰神经网络
计算机硬件
管道(软件)
电子工程
像素
计算
内存带宽
CMOS芯片
钥匙(锁)
人工神经网络
串行解串
图像处理
数据采集
实时计算
时钟频率
Spike(软件开发)
并行处理
专用集成电路
超大规模集成
电效率
嵌入式系统
能源消耗
核电子学
数据处理
芯片上的系统
目标检测
功率(物理)
作者
De Xu,Zhaoqi Miao,Guanhong Zheng,Musheer Abdullah,Shengbo Lin,Wu Gao
出处
期刊:IEEE Transactions on Circuits and Systems I-regular Papers
[Institute of Electrical and Electronics Engineers]
日期:2026-03-31
卷期号:73 (8): 5266-5279
标识
DOI:10.1109/tcsi.2026.3677391
摘要
The use of neural networks for processing X-ray detector data has become a key development trend in high-energy physics and medical imaging. As detector arrays grow, handling the resulting massive data volumes poses significant challenges in terms of system bandwidth and power consumption. To address the bandwidth bottleneck and high analog-to-digital conversion (ADC) power consumption in conventional X-ray imaging systems, we propose an in-sensor computing architecture, SpikeX, for accelerating spiking neural networks (SNN). First, a photon-counting analog front end is directly integrated with pixel-level SNN neurons, enabling the first convolutional layer to be computed using spike signals. This eliminates the need for analog-to-digital conversion, significantly reducing power and bandwidth requirements. Next, an event-driven on-chip SNN accelerator performs efficient temporal inference, enabling an end-to-end pipeline from signal acquisition to image classification. Furthermore, detector non-idealities can be absorbed by the SNN model during training. To systematically investigate these effects, we develop a signal processing algorithm, enabling effective correction of detector non-idealities. To validate the proposed architecture, we implemented the SpikeX using a 180 nm CMOS process, featuring a$28\times 28$pixel array and 32 Leaky Integrate-and-Fire (LIF) processing units. Simulation results show that, at a clock frequency of 50 MHz, the architecture achieves an energy efficiency of 1.88 TOPS/W, significantly outperforming comparable state-of-the-art designs.
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