Design of Area-Efficient, Low-Quiescent-Current LDOs for Chip-Level Power Management

In this paper, design methodology of area-efficient and low-quiescent-current low-dropout regulators (LDOs) for chip-level power management is proposed. As LDO chip size is dominated by the large size power transistor, guidelines are given to minimize its size when design specifications such as the dropout voltage, the minimum input voltage and the maximum load current are given. The reduced power transistor size also helps to maintain satisfactory error amplifier slew-rate at low quiescent current consumption. Stability of LDO designed under the proposed methodology is thoroughly studied. Extensive simulations are done to verify the stability study.