Large‐Scale Vertically Interconnected Complementary Field‐Effect Transistors Based on Thermal Evaporation

Abstract With the rapid development of integrated circuits, there is an increasing need to boost transistor density. In addition to shrinking the device size to the atomic scale, vertically stacked interlayer interconnection technology is also an effective solution. However, realizing large‐scale vertically interconnected complementary field‐effect transistors (CFETs) has never been easy. Currently‐used semiconductor channel synthesis and doping technologies often suffer from complex fabrication processes, poor vertical integration, low device yield, and inability to large‐scale production. Here, a method to prepare large‐scale vertically interconnected CFETs based on a thermal evaporation process is reported. Thermally‐evaporated etching‐free Te and Bi 2 S 3 serve as p ‐type and n ‐type semiconductor channels and exhibit FET on‐off ratios of 10 3 and 10 5 , respectively. The vertically interconnected CFET inverter exhibits a clear switching behavior with a voltage gain of 17 at a 4 V supply voltage and a device yield of 100%. Based on the ability of thermal evaporation to prepare large‐scale uniform semiconductor channels on arbitrary surfaces, repeated upward manufacturing can realize multi‐level interlayer interconnection integrated circuits.