计算机科学
现场可编程门阵列
硬件加速
光流
计算机硬件
人工神经网络
设计流量
二进制数
多路复用
计算机工程
特征(语言学)
实时计算
人工智能
嵌入式系统
图像(数学)
电信
算术
哲学
语言学
数学
作者
Yuanxing Yan,Yehua Ling,Kai Huang,Gang Chen
标识
DOI:10.1016/j.sysarc.2022.102818
摘要
Recently, accelerator architectures of deep neural networks (DNNs) have been designed to accelerate computer vision tasks, gaining the advantages of both accuracy and speed. However, DNNs-based optical flow estimation accelerators have not been successfully deployed due to the resource constraint. Existing hardware accelerators for optical flow estimation are all designed for non-DNN methods and generally perform poorly in estimated accuracy. In this paper, we present FlowAcc, a dedicated hardware accelerator for DNN-based optical flow estimation, adopting a pipelined hardware design for the real-time processing of image streams. We design an efficient multiplexing binary neural network (BNN) architecture for pyramidal feature extraction to significantly reduce the hardware cost and make it independent of the pyramid-level number. Furthermore, efficient designs such as hamming distance calculation and competent flow regularization are used for hierarchical optical flow estimation to greatly improve the system’s efficiency. Comprehensive experimental results demonstrate that FlowAcc achieves state-of-the-art estimation accuracy and real-time performance on the Middlebury dataset when compared with the existing optical flow accelerators.
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