计算机科学
量化(信号处理)
算法
推论
断层(地质)
人工智能
故障检测与隔离
GSM演进的增强数据速率
边缘检测
模式识别(心理学)
信号处理
噪声测量
边缘设备
算法设计
数据压缩
数据建模
离散余弦变换
模糊推理
作者
Zhuolin Bao,Xiaofei Zhang,Heng Shan,Jianyu Fang,Zeping Wu,Yunze He,Guojun Qin,Weizhi Liang
标识
DOI:10.1109/jiot.2026.3701897
摘要
Lightweight fault diagnosis (FD) models are essential for efficient inference on resource-constrained IoT edge devices and practical industrial deployment. While existing lightweight FD research has achieved notable progress in network architecture compression, the substantial benefits brought by quantization techniques remain largely overlooked. However, directly applying mainstream quantization methods to FD tasks is problematic, as they suffer from two main drawbacks: 1) Uniform quantization struggles to simultaneously maintain local resolution in dense regions and dynamic range coverage in sparse regions. 2) Mainstream quantization-aware training (QAT) methods rely on the straight-through estimator (STE) to approximate discrete gradients, introducing gradient bias that further limits model accuracy improvement. To address these issues, this paper proposes an Adaptive Quantization Error Minimization Method (AQEMM) for fault diagnosis, with the following main contributions: 1) An adaptive quantizer is introduced to replace the traditional fixed quantization step size, expanding the search space of quantization points from discrete integer grids to a continuous subspace, enabling quantization levels to adaptively concentrate in data-dense regions. 2) A block coordinate descent strategy is incorporated to alternately optimize quantization parameters, with quantization reconstruction error minimization as the direct optimization objective, fundamentally circumventing the gradient bias introduced by STE. Validation on FD tasks for two typical industrial devices, induction motors (IM) and permanent magnet synchronous motors (PMSM), demonstrates that the proposed 2-bit quantization model saves up to approximately 82% of hardware resources compared to full-precision (FP) deployment on an FPGA platform while maintaining competitive diagnostic accuracy. Furthermore, by optimizing the hardware design to leverage the released hardware resource margin, a significant inference speedup of approximately 20.6× is achieved over pure software inference.
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