A Separated Pre-Charge Sense Amplifier With Fast Sensing, Low Power, Small Area, and High Reliability for Hybrid MTJ/CMOS Logic Circuits

The use of logic circuits combined with emerging devices has been studied to overcome the limitations of complementary metal-oxide-semiconductor (CMOS) transistors. Among a variety of emerging devices, magnetic tunnel junction (MTJ) is a promising candidate owing to its non-volatility, high endurance, and CMOS compatibility. However, process variations in MTJs and CMOS transistors hinder reliable and precise resistance-to-voltage conversion in hybrid MTJ/CMOS logic circuits. To address this issue, this paper proposes a novel separated pre-charge sense amplifier that achieves fast-sensing, low-power, small-area, and high-reliability. The proposed circuit eliminates intermediate inverters between the discharge and evaluation stages. It incorporates P-channel MOS (PMOS) transistors within the inverter latch, whose gates are directly biased by voltages that reflect the resistance difference between a pair of MTJs. It minimizes its nodes to be charged or discharged during operation. Furthermore, it reduces the total transistor count, including clock-driven transistors. Simulations are performed using Cadence and HSPICE tools with the NCSU CMOS 45nm design kit and a physics-based MTJ SPICE model. Monte Carlo simulations are conducted to check the circuit’s reliability under process, voltage, and temperature (PVT) variations. Post-layout simulation results show that the proposed circuit achieves the fastest sensing delay among the compared circuits except for Separated Pre-Charge Sense Amplifier (SPCSA), lowest power consumption, lowest power-delay product, smallest area overhead, and lowest sensing error rate for a viable usage in hybrid MTJ/CMOS logic memory circuits.