2D Short‐Channel Tunneling Transistor Relying on Dual‐Gate Modulation for Integrated Circuits Application

Abstract With continuous size scaling, the surface dangling bonds and short‐channel effects will degrade silicon based transistor performance. Thus, it is of great importance to seek new channel materials and transistor architectures to further continue Moore's law. Herein, a new ultra‐thin short‐channel tunneling transistor is developed comprising all 2D‐ components. Distinct from usual 2D planar transistor, this device is configured with vertical MoS 2 /WSe 2 junction and in‐plane WSe 2 channel, the switch states are realized by the gate‐regulated barrier height of heterojunction, enabling the transition of transport mechanism between thermionic‐emission and tunneling. Under dual‐gate configuration, the transistor exhibits high performance with drive current of 4.58 µA, on/off ratio of 4 × 10 7 , subthreshold swing (SS) of 97 mV decade −1 and drain‐induced barrier lowering (DIBL) of 12 mV V −1 , that can meet the requirement of logical applications in integrated circuits (IC). Taking advantage of the high‐speed tunneling current and unique short‐channel architecture, the device overcomes the issues of voltage spikes and long reverse recovery time that exist in usual electric components, and thus gains an access to the IC interface. This work provides a proof‐of‐concept transistor architecture relying on dual‐gate modulation, opening up a promising perspective for next generation low‐power, high‐density, and large‐scale IC technologies.