Device property and parameter trade-off study for a photonic spin register based on magnetic tunnel junctions for high-speed link applications

Abstract We present a new approach to high-speed link design based on magnetic tunnel junction (MTJ) devices placed in an array to form a photonic spin register (PSR). After discussing the characteristics and operating principle of the PSR, we investigate the trade-offs involved in designing an electrical interface to read data from it. The variables considered are device noise, input-referred noise of comparators in the read-out circuits, power consumption, and data rate. We also depict the relations among multiple variables in a compact way, showing that comparator power constitutes the dominant portion of the overall power consumption. Also, starting with relatively low data rates (10's of Gb/s) as a first step, we estimate that post–forward error correction (FEC) bit error rates (BERs) of less than 10 −15 are possible with an energy efficiency in the order of 10's of fJ/bit.