A Low-Power 8-GS/s Comparator for High-Speed Analog-to-Digital Conversion in $0.13\mu$ m CMOS Technology

This brief presents a novel comparator circuit design for high-speed analog-to-digital converters in data communication systems. The circuit achieves higher bandwidth compared to existing architectures, without the use of bandwidth enhancing inductors. Implemented in 0.13μm CMOS technology, the proposed comparator operates from a 1.2V supply and consumes a total power of 2.4mW, with sampling speeds up to 8-GS/s.