Unified Analysis, Modeling, and Simulation of Chopping Artifacts in Continuous-Time Delta-Sigma Modulators

Chopping is an efficient way of mitigating the effect of flicker noise in continuous-time delta-sigma modulators (CTDSM). Unfortunately, chopping causes the demodulation of shaped quantization noise into the signal band. Prior works have analyzed noise-folding effects in chopped integrators that use single-stage and two-stage feedforward-compensated OTAs. These works use restrictive assumptions, like settling of the OTA internal nodes at the chopping instants, and an NRZ feedback DAC waveform. This work gives a general model for aliasing of shaped noise in a chopped integrator that incorporates arbitrary OTAs, arbitrary DAC pulse-shapes, and incomplete settling. Using the theory of linear periodically time-varying (LPTV) systems, we derive a simple simulation test-bench that can be used to estimate the parameters of our model. Thanks to this, the effects on chopping on the performance of the modulator can be rapidly estimated without running long transient simulations. Simulation and experimental results that support our theory are given.