Analytical model for thermal instability of low voltage power MOS and SOA in pulse operation

Thermal instability presented by some high current power MOS has been shown to limit significantly the SOA capability. In this paper, we present a new analytical model to explain this type of instability in transient operation, based on an analytical formulation for both the positive temperature coefficient of the drain current and for the thermal resistance. The model is capable of predicting the onset of thermal instability for a given device structure and layout, and can be used both to define the allowed SOA of the device and as a design guide to design more rugged devices.