Thermal Improvement of HBM with Joint Thermal Resistance Reduction for Scaling 12 Stacks and Beyond

As the demands for implementing High Performance Computing (HPC) increase rapidly, the bandwidth and capacity required for High Bandwidth Memory (HBM) are expected to increase by two to three times per generation. Owing to these increased requirements, the power of the next HBM is expected to exceed 30W, and the number of stacks of the HBM leads to a high-level stack demand of 12 and beyond, which also increases the physical thermal resistance of the HBM. Therefore, it is inevitable to strive to improve the thermal performance of HBM. Herein, we demonstrate thermally enhanced joint of HBM with state-of-the-art Thermocompression (TC) bonding. We found that the joint thermal resistance with TC was 35% less than that with Mass reflow (MR) bonding because the joint thickness reduction is more effective to reduce the resistance and that is possible with TC. In addition, even when the joint thermal resistance is almost zero by applying the Hybrid Copper Bonding (HCB), thermal challenge is still exist in the case of high-level stack and high power condition. Therefore, we added analysis on how to operate the HBM below the refresh limit temperature with solution and conditions such as power reduction, on-chip optimization and temperature sensor location.