Numerical Investigation on the Influence of Voiding in Indium-Based Thermal Interface Materials for Thermal Performance in Flip-Chip Packages

This study systematically explores the mechanism by which void defects in the interface layer of indium-based thermal interface materials affect the thermal reliability of flip chip ball grid array (FCBGA) packaging during successive reflow cycles. Utilizing heat-flow coupling theory, we developed a three-dimensional thermal numerical model to investigate the synergistic effects of void geometry (size, number, and distribution density), spatial arrangement, and heat-source non-uniformity on the thermal stability of the package. Through Taguchi orthogonal experimental design and variance analysis, the results show that the weights of the void characteristic parameters on the junction temperature are void geometric size, spacing and number. To further quantify the impact of void within the solder layer, thermal resistance and the uniformity of the heat source surface temperature were adopted as characterization metrics. The results demonstrate that increasing porosity from 0 to 10% induces an approximately 1.5 °C change in the chip’s surface temperature. Despite a 10 % increase in porosity yielding only a modest 1.5 °C rise in the chip surface temperature gradient, the spatial arrangement of voids relative to the heat source markedly influences the overall thermal field distribution. The simulations indicate that as the void-heat-source center offset grows, the peak junction temperature deviation spans approximately 5.9 to 20.24 °C. By developing a multi-parameter coupled thermal-resistance model, this study elucidates the fundamental mechanisms by which void defects undermine the thermal stability of packaging modules, thereby furnishing a solid theoretical basis for the optimal design of high-reliability electronic packaging structures.