Realizing Logic Functions Using Single Double-Gate Tunnel FETs: A Simulation Study
作者
Saptak Banerjee,Shelly Garg,Sneh Saurabh
出处
期刊:IEEE Electron Device Letters [Institute of Electrical and Electronics Engineers] 日期:2018-03-26卷期号:39 (5): 773-776被引量:32
标识
DOI:10.1109/led.2018.2819205
摘要
In this letter, a single double-gate tunnel field-effect transistor (DGTFET) is proposed to realize different logic functions and investigated using two-dimensional device simulations. It is shown that a single DGTFET can realize logic functions, such as AND, OR, NAND, and NOR by biasing the two gates independently. The key elements in obtaining different logic functions using a DGTFET are employing a gate-source overlap and choosing an appropriate silicon body thickness. Furthermore, it is demonstrated that two-input CMOS-type AND, OR, NAND, and NOR logic gates can be implemented using two DGTFETs that are designed to exhibit complimentary logic functions.