Digitally assisted quasi-V2 hysteretic buck converter with fixed frequency and without using large-ESR capacitor

The rapid advancement of processor technology has posed stringent challenges on power supply design. For high efficiency, switching converters are used. Frequent load switching requires the converters to have fast load transient response with recovery times in the order of mus, and therefore the switching frequency in the MHz range. The transient overshoot and undershoot voltages must be within 10% of the output voltage, and such specifications are difficult to meet for a processor core voltage of 0.8V. For fast load transient, inductor current should be fed forward to the PWM generator, which needs a high performance integrated current sensor. In the output feedforward (or V ² ) converter, inductor current is sensed by the equivalent series resistor (ESR) of the output capacitor instead. The generic implementation of a V ² buck converter is shown in paper. The output voltage, V ₀ , is fed back to the error-correction path (ECP) for precision output voltage control, and V ₀ is also directly fed to the PWM generator through the feedforward path (FFP). It is shown that the output voltage ripple, DeltaV ₀ , is dominated by Deltal _lscr timesR _ESR , and any change in V ₀ requires the PWM generator to adjust the inductor current immediately, thus speeding up the response. However, to make sure that the V ² converter operates properly without pulse skipping, a large ESR is needed. To eliminate a large ESR, a derivative-output-voltage (DOV) technique is suggested, to extract the inductor current ripple through differentiating V ₀ . However, V ₀ is a noisy node and is affected by frequent load changes, and therefore obtaining accurate current information is challenging.