Design and stress analysis for fine pitch flip chip packages with copper column interconnects

As the demand for high input/output (I/O) density, package miniaturization, high frequency operation and better thermal, mechanical and electric performance increases, flip chip packaging technology is rapidly growing as a solution to successfully achieve these goals. With handheld electronic devices, hot consumer products, graphics cards and memory packages in high demand, fine pitch flip chip packages (fcFBGAs) with bond-on-lead (BOL) interconnection are increasingly being pursued and widely studied in the electronic industry. BOL technology uses copper (Cu) column bumps that attach to narrow pads or traces without any solder resist confinement (open solder resist (SR)) in the peripheral I/O region of the die as opposed to a conventional circular bond-on-capture pad (BOC) structure. The BOL interconnection enables significantly higher routing densities at a lower cost for a given set of design rules. Although the advanced BOL packaging structure has been proven to have high stress resistance in extremely low-k (ELK) layers which prevents damage in finer silicon nodes, the increased risk of Cu trace peeling and/or Aluminum (Al) pad/under bump metallization (UBM) layer delamination can be caused by excess stresses. It is important to study these failure phenomena in 28-nm ELK fcFBGA with copper column interconnects. For the purpose of validating possible failure types in the 28-nm ELK fcFBGA with Cu column BOL interconnects, the three-dimensional finite element analysis (FEA) was adopted. The stress responses for each of the components were also obtained to determine the critical area that may potentially result in failures in this structure. Furthermore, to reduce the critical stress and enhance the reliability in a 28-nm ELK fcFBGA with Cu column BOL interconnects, a parametric discussion that captures the most significant factors impacting the stresses was studied. The result of this study provides a superior design for stress reduction to lower the risks of Cu trace peeling, Al pad/UBM delamination and ELK damage. Through this study, FEA simulations and corresponding validations can help to prevent the critical failure issues that are impacted by improper material and geometry designs in 28-nm ELK fcFBGA with Cu column BOL interconnects.