AltPSM is a leading contender for the gate layer lithography at 65 nm, and perhaps additional layers at 45 nm. Every form of lithography varies in performance across dose and focus, but altPSM lithography also is subject to the impact of mask alignment and effective phase. In the past, these factors have been maintained to an acceptable level to achieve the required ACLV over an acceptable process window for the designs that warranted the additional expense of altPSM. As the ACLV requirements continue to shrink along with feature size, the control of these variables must also be tightened. This paper will illustrate a methodology of using silicon-calibrated models coupled with real layout to predict the variation in ACLV due to each of these process variations.