Scaling of parasitics in mm-wave MODFETs

Parasitics must be reduced for mm-wave MODFETs to realize their high potential. The parasitic resistances must be reduced so that (1) parasitic charging time is negligible, (2) to maintain the fj/fmax ratio, and (3) noise figure and power performance are not degraded significantly. The parasitic resistance must be scaled as l/fj. The problem of backside via inductance dominating the effective input resistance of wide MODFETs is shown. The design compromises are discussed, and rules-of-thumb are presented for scaling parasitics, (e.g., T-gate size).