Faster switching with less overvoltage - operating a SiC-MOSFET at its speed limit

This paper explores the turn-off switching behavior of a third-generation SiC MOSFET encapsulated in a TO-247-4 package. The work is focused on the selection of the optimal gate resistance to reduce the turn-off switching losses. The selection criteria is based on the limitation of the inductive over-voltage peak (OVPK) for the worst-case scenario i.e. maximum DC-link voltage and switched current. The gate resistance is tuned to induce the allowed OVPK, gradually, with decreasing gate resistance the switching losses would be reduced but the OVPK would increase. Contrary to the expected behavior, it is observed that there exists a threshold value from which, the decrease of the gate resistor reduces the OVPK and, moreover, the turn-off losses do also decrease.