Patterns of Exposing Integrity of 28nm-node High-k Gate Dielectric on p-substrate with Nitridation Treatments

Well-designed test patters are useful to investigate the integrity of gate dielectric, especially in advanced nano-node process technology with high-k Hf-based dielectric. Besides monitoring the growth of gate dielectric, the antenna effect coming from the back-end of line (BEOL) process or etch contribution can be detected through the demonstration of electrical performance of sub-threshold voltage, interface-state density, and gate leakage. Adopting the capacitance-voltage (C-V) and gate leakage measurement, the integrity of high-k gate dielectric with the assistance of fringe and area patterns can be reflected. This study mainly focused on gate dielectric on p-substrate with the electrical measurement. Through the data analysis, we also performed the performance comparison with various annealing temperature as nitridation treatment.