CMOS芯片
相位噪声
锁相环
电子工程
计算机科学
压控振荡器
频率合成器
噪音(视频)
电气工程
dBc公司
收发机
闪烁噪声
三角积分调变
线性
滤波器(信号处理)
作者
Chen Mingyi,Chu Xiaojie,Yu Peng,Yan Jun,Shi Yin
出处
期刊:Journal of Semiconductors
[IOP Publishing]
日期:2013-10-01
卷期号:34 (10): 105001-
被引量:1
标识
DOI:10.1088/1674-4926/34/10/105001
摘要
A fully integrated ΔΣ fractional-N frequency synthesizer fabricated in a 55 nm CMOS technology is presented for the application of IEEE 802.11b/g wireless local area network (WLAN) transceivers. A low noise filter, occupying a small die area, whose power supply is given by a high PSRR and low noise LDO regulator, is integrated on chip. The proposed synthesizer needs no off-chip components and occupies an area of 0.72 mm2 excluding PAD. Measurement results show that in all channels, the phase noise of the synthesizer achieves −99 dBc/Hz and −119 dBc/Hz in band and out of band respectively with a reference frequency of 40 MHz and a loop bandwidth of 200 kHz. The integrated RMS phase error is no more than 0.6°. The proposed synthesizer consumes a total power of 15.6 mW.
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