Fan-out panel-level package warpage and reliability analyses considering the fabrication process

材料科学 可靠性(半导体) 制作 过程(计算) 可靠性工程 机械工程 复合材料 工程制图 计算机科学 工程类 医学 功率(物理) 物理 替代医学 病理 量子力学 操作系统
作者
Chia-Wei Liang,Yu-Chi Sung,Sheng‐Jye Hwang,Ming-Hsiang Shih,Wen‐Hsiang Liao,Te-Hsun Lin,Dongyan Yang
出处
期刊:Journal of Manufacturing Processes [Elsevier BV]
卷期号:119: 649-665 被引量:26
标识
DOI:10.1016/j.jmapro.2024.03.070
摘要

With the continuous advancement of IC packaging technology, 3D and 2.5D packaging systems have emerged as the prevailing trends. The advantages of large area and high I/O density have made fan-out panel-level packaging (FOPLP) been considered as one of the best package types for 3D and 2.5D packaging applications. The discussions about FOPLP have been popular recently. Warpage and reliability of FOPLP are the main concerns of packaging engineers. However, it was found that warpage and reliability of FOPLP are strongly related to the fabrication process but not many research works have been published. Thus, reliability analysis procedure considering the residual stress of fabrication process was proposed in this paper to observe warpage and stress distribution during fabrication process. Then, this research procedure facilitates subsequent fatigue life calculations and predicts reliability of the package. First, the thermal stresses and warpage of the redistribution layer-first (RDL-first) process were conducted for an entire panel. Next, warpage and thermal stress analyses were conducted for a strip encapsulated with an epoxy molding compound (EMC) during compression molding. Then, a reliability analysis was conducted with an IC unit and incorporated the consideration of the residual stress induced during the fabrication processes. The compression molding analysis utilized the pressure–volume–temperature–cure (P–V–T–C) model to account for both the volume shrinkage caused by a thermal mismatch and the chemical shrinkage. Furthermore, dual shift factor model was used to model the viscoelastic behavior of EMC in this study during PMC analysis effectively. An observation of the stress distribution for an IC unit revealed that the maximum stress position was at the solder ball near the periphery, with a stress value of 147.309 MPa. The fatigue life calculated using the modified Coffin–Manson fatigue model was 417 cycles.
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