Rational Fabrication of Dual-Channel Layered InGaSnO Thin-Film Transistors Through High-/Low-Power Sputtering Technique

In this study, the high/low power sputtered dual-channel structured InGaSnO thin-film transistors (TFTs) were fabricated, and their electrical performance and stability were also studied. As a result, the deposited high/low power (120/60 W) dual-channel structured InGaSnO TFTs exhibited the best electrical performance, which included the $\mu _{\text {FE}}$ of 32.8 cm²/Vs, small subthreshold slope (SS) value of 0.36 V/decade, small ${V}_{\text {th}}$ of 0.2 V, low ${N}_{T}$ value of $1.1\times 10^{{12}}$ cm ${}^{-{2}}$ /eV, and high ${I}_{\text {on}}/{I}_{\text {off}}$ of $10^{{7}}$ , respectively. In this dual-channel structured device, the 6-nm high power (120 W) ultrathin layer InGaSnO provides free carriers for the channel layer, resulting in increased mobility. Also, the 20-nm low-power (60 W) thick InGaSnO layer can control the ${V}_{\text {th}}$ through the formation of a potential barrier (0.45eV). Moreover, the deposited (120/60 W) bilayer structured InGaSnO TFT with Al₂O₃ passivation layer (PVL) also showed robust stability with small ${V}_{\text {th}}$ shifts of 0.7 and −0.8 V during 60-min time positive bias illumination stress (PBIS) and negative bias illumination stress (NBIS) measurements. Overall, the deposited (120/60 W) dual-channel structured InGaSnO TFT with Al₂O₃ PVL has opened a new way and a simple method to achieve high-performance oxide TFTs for applications in flat-panel displays.