Parasitic Conduction on Ω-Gate Nanowires SOI nMOSFETs

The Ω-Gate nanowire (NW) SOI nMOSFETs is an excellent candidate for future technology nodes. The goal of this work is to study the Ω-Gate NW SOI nMOSFET working in subthreshold region for low-power low-voltage (LPLV) application, with special attention on a possible parasitic drain current conduction. The studied devices are Ω-Gate nanowires SOI nMOSFETs that were fabricated at CEA-LETI/France with the following characteristics: the effective oxide thickness (EOT) of 1.3nm, the buried oxide thickness (t oxb ) of 145nm and the channel height (H fin ) of 10nm with three channel widths (W fin ) 220, 40 and 10nm and four channel lengths (L) 40, 100, 200nm and 1µm. Figure 1 presents the curve of the drain current (I DS ) as a function of gate voltage (V GS ) from which the electrical parameters such as threshold voltage (V T ) and subthreshold swing (SS) (Fig.2) were extracted. From figure 2 it is possible to see that short channel devices present a SS degradation as well as present a V T variation for all channel widths, improving for narrow width as expected. However, focusing on V T behavior, an abnormal reduction on the V T values is observed for wider channel width even for long devices. Aiming to better understand this unexpected behavior, some simulations were performed using TCAD Sentaurus, Synopsis ® . Figure 3, shows the simulated transfer curve for device with the same characteristics of the experimental. It is observed that it was necessary to insert the interface charges of 5x10 11 cm -3 to have a good agreement of the simulated with the experimental data. Figure 4 shows the simulated I­ DS xV GS for several different fixed interface charges on the back interface (channel/buried oxide) in order to simulate a radiation effect on the devices. The interface charges were varied from 5x10 11 cm -3 up to 1x10 13 cm -3 . Based on the simulations it is possible to notice that the increase of interface charges causes a parasitic conduction from drain to source at the back interface. Aiming to analyze the back conduction, three different values of I DS were adopted , as can be seen in figure 4B. Analyzing the current density on the front and back interface in figure 5, it can be noted that on the first point, that is located on the subthreshold slope (fig.5A), the conduction is mainly composed by the back interface for all fixed charges level. When getting closer to V T (Fig.5B) the conduction by the front interface starts to increase but the device characteristics is still affect by the back conduction and then after V T (Fig.5C) the front interface predominates. The transition of predominant conduction from the back to the front interface usually causes an abnormal I DS behavior that can be seen in the inset presented in figure 4B, where a kind of kink is clearly observed in the curves which the fixed charges is higher than 3x10 12 cm -3 . Since the EOT is very thin, and the H fin is 11nm, for fixed charges smaller than 3x10 12 cm -3 the usual behavior degradation caused by back conduction (the SS increase or a hump in the subthreshold region) is not observed in the simulated results. This unexpected result can be explained by the theoretical values of SS for the two different situations: 1) front or 2) back interface conduction, presenting an insignificant variation between the front and back SS values. This behavior can also be observed from the extracted SS values from the simulations varying the fixed charges, presented in table 1. This SS immunity to back conduction happens because these devices have a very good coupling between the interfaces due to the thinner EOT. Although this device presents a higher SS immunity, the back interface conduction occurs early as the channel width becomes wider, resulting in smaller V T for all channel lengths. This behavior is more pronounced as the fixed charge increases on the back interface. This behavior can also explain the reduction on V T values for wider devices presented on the experimental results (Fig.2). The simulated fixed charges on the back interface, can represent the radiation effects on these devices, due to the thinner gate oxide, and as was showed it did not affect the SS significantly. Therefore, when thinking about operation on the subthreshold region, where the current is exponentially proportional to V GS , the devices with narrow width are the most recommended, due to the better control of the charges in the channel but since the channel is long enough to avoid the short channel effects. And as the back conduction did not affect the SS these devices are also able to operate in irradiated environments. Figure 1