| 标题 |
A Novel 3D AND-Type 1T1C DRAM Architecture with Local Bitline Transistor (BLT) to Reduce the Bitline Capacitance (CBL) for Enhanced Sensing Window in High-Layer Stacked 3D DRAM |
| 网址 | |
| DOI |
10.1109/IMW68301.2026.11532892
doi
|
| 其它 |
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(2025-6-4)