An Analytical Approach to Study the Impact of Traps on Ge-Source Double Gate PNPN TFET

The analytical models for surface potential, electric field, and drain current of a Ge-source double gate hetero-structure PNPN Tunnel FET are developed taking into account the oxide-semiconductor interfacial trap charges. Although other researchers have used similar modeling techniques on various structures, the proposed structure has not yet utilized them when considering the source/drain depletion region and interfacial trap charges that reflect changes in the flat band voltage. The proposed device consists of Ge-source, Si1−xGex pocket (mole fraction 0.3), and Si channel and drain. Moreover, the non-uniform concentration of trap charges is considered at the oxide/semiconductor interfaces: 1013 cm−2 at HfO2/ Si1−xGex interface and 1012 cm−2 at HfO2/Si interface. 2D Poisson's equation is solved with the help of parabolic potential approximation and different boundary conditions to develop the surface potential model. The developed potential model is subsequently used to construct the electric field model. The drain current model of the proposed TFET is finally developed with the help of the generated electric field and some other parameters. All the developed models are validated using TCAD-simulated data. The studies show that there is good agreement between the simulated and modeled results, ensuring the applicability of the device in charge-trapped memory systems based on tunneling.