Low-thermal surface preparation, HCl etch and Si/SiGe selective epitaxy on (1 1 0) silicon surfaces

We have first investigated the influence of the in situ H2 bake temperature (between 750 ?C and 850 ?C) on (1?0?0) and (1?1?0) fullsheet surface preparations (after 'HF-last' wet cleaning). A strong increase of the (1?1?0) surface roughness occurred when baking between 750 and 775 ?C, with high C and O contamination peaks at the Si substrate/Si overlayer interface. A high H2 bake temperature (?800 ?C) is thus mandatory for both (1?0?0) and (1?1?0) Si surfaces. We have also studied the 750 ?C?950 ?C, high HCl partial pressure etch of blanket Si wafers. HCl etch rates are roughly four times higher on (1?1?0) than on (1?0?0). Etch rate activation energies are however quite close to each other (57 kcal mol?1 on (1?0?0) ? 59 kcal mol?1 on (1?0?0)), suggesting similar etch-limiting mechanisms. We have then investigated the low-temperature growth of high Ge content (10?37%) SiGe layers on blanket Si wafers with dichlorosilane + germane chemistry (selective versus SiO2 on patterned wafers). The SiGe growth rate on (1?1?0) bows downwards from linearity and then saturates when increasing the germane mass flow. In contrast, it almost linearly increases on (1?0?0) surfaces, reaching values more than three times higher than on (1?1?0). A parabolic relationship between experimental Ge concentrations and the F(GeH4)/F(SiH2Cl2) mass-flow ratio has been evidenced on (1?0?0). In contrast, a linear relationship links the (1?1?0) Ge concentration to the F(GeH4)/F(SiH2Cl2) mass-flow ratio. Finally, 63 and 65 kcal mol?1 activation energies are associated with the fullsheet Si growth rate increase with the inverse absolute temperature on (1?0?0) and (1?1?0) (dichlorosilane chemistry). The GR(1?1?0)/GR(1?0?0) Si growth rate ratio, ?0.74, is close to the dangling bond surface density (DBSD) ratio (DBSD(1?1?0)/DBSD(1?0?0) ? 0.71). Such growth rate discrepancies are thus justified by these DBSD differences. Results obtained on fullsheet wafers have been used to selectively grow SiGe/Si stacks on (1?0?0) and (1?1?0) patterned Si wafers for silicon-on-nothing and localized-silicon-on-insulator purposes, respectively.