Scalable high-order integrated photonic tensor processor via frequency-domain modulation

The rising computational demands of deep learning—particularly for high-order tensor operations—have driven the need for novel hardware accelerators. While integrated photonics presents a promising platform, the matrix scale of existing schemes is often constrained by the physical number of on-chip components. Here, we propose and experimentally demonstrate a scalable high-order integrated photonic tensor processor (HIPTP) that decouples the computational dimensionality from physical device count by leveraging a two-dimensional array combined with electrical frequency-domain modulation. The design employs a scalable array of cascaded Mach–Zehnder interferometers (MZIs) and photodetectors (PDs), enabling third- and fourth-order tensor multiplication by encoding data onto distinct microwave frequencies. A 4×4 HIPTP chip was fabricated and characterized, exhibiting high consistency across core components, which facilitates the extension toward larger-scale on-chip systems. To validate its computational capabilities, three computational modes were verified under varying frequency counts, and an inference accuracy of 97.5% was achieved on the German traffic sign recognition benchmark (GTSRB). Our work presents a promising pathway toward ultra-large-scale photonic computing for advanced AI models and frequency-aware signal processing scenarios.