Bit-Cost-Scalable 3D DRAM Architecture and Unit Cell First Demonstrated with Integrated Gate-Around and Channel-Around IGZO FETs

Novel 3D DRAM architectures with 2T0C IGZO gain cell and bit-cost-scalable 3D array process are proposed and demonstrated for the first time. The unit cell is composed of one gate-around (GA) FET and one channel-around (CA) FET to form the 2T0C memory device, where the GA FET and CA FET serve as the write transistor and the read transistor for the DRAM cell, respectively. To verify the possibility of this 3D stacking architecture, we demonstrate the GA IGZO FET by top metal gate with IGZO channel structure, and the CA IGZO FET by bottom IGZO gate with IGZO channel. The integrated 2T0C 3D DRAM memory cell shows excellent device characteristics with>180 second data retention time and endures>1000 second DC stress on the write and read transistors w/o memory window closure. The proposed backend-of-line compact 2T0C DRAM cell features small footprint, bit-cost scalable 3D array, fast write/read, and good reliability, which is promising for future high density embedded memory applications.