High-NA EUV mask CD-SEM metrology matching, and contour-based comparison of simulation result and wafer print

薄脆饼 极紫外光刻 计量学 计算机科学 匹配(统计) 材料科学 光学 人工智能 光电子学 物理 数学 统计
作者
Joost Bekaert,Jirka Schatz,Sotaro Hosoya,Hideaki Komami,Syamashree Roy,Guillaume Libeert,Balakumar Baskaran,Vicky Philipsen,Eric Hendrickx,Darko Trivković,Ulrich Welling,Shosuke Tomizuka,Masataka Yamaji,Tatsuya Tomita,Nobuaki Fujii,Shingo Yoshikawa,Hideki Nakaya,Toshimichi Iwai,Tatsuro Okawa,Wataru Ito
标识
DOI:10.1117/12.3072600
摘要

ASML’s first High-NA EUV scanners with 0.55 NA optics are operational. The wafer printing performance is being evaluated and enhanced within the ecosystem of the imec-ASML High-NA lab. Due to the anamorphic optics, High-NA EUV masks are designed at (4x,-8x) magnification compared to wafer scale. Consequently, while mask dimensions further shrink to unprecedented resolution in X-direction, they relax in Y-direction, resulting in asymmetric mask patterns, with new mask perceptions and mask challenges which become dependent on pattern orientation. Meanwhile, at stringent dimensions, CD errors at mask must be further reduced. Moreover, due to the anamorphic optics, even a symmetric CD offset at mask leads to an asymmetric CD error on the wafer. In this context, updating mask metrology alignment between different parties in the litho process is critical in order to minimize mask CD errors originating from differences in metrology conditions. In this paper, we present the outcome after matching the mask CD-SEM conditions between imec’s and a mask maker’s CD-SEM tool, as well as mask metrology alignment with EDA software, since agreement between these parties is essential for achieving a consistent litho process flow from design and OPC, over mask making and metrology, to wafer print. With alignment on optimized settings for metrology on (High-NA) EUV masks, we demonstrate that an excellent match in mask metrology can be achieved. Subsequently, we demonstrate rigorous simulation for a High- NA EUV use-case, based on measured mask contours. Finally, the simulation outcome is compared to High-NA wafer data by means of edge placement evaluation, showing very good correspondence between simulated and measured in-resist contours. This demonstrates how contour-based rigorous simulation and edge placement evaluation are valuable tools for investigating the contribution of the mask to the wafer printing, and assessing the lithographic performance under different exposure conditions, thereby helping to optimize the High-NA EUV lithography process.
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