Embedded tutorial: Fundamentals and advances in jitter analysis of high-speed links

For high speed links, it is essential to meet the voltage and timing margin to achieve the Bit-Error-Rate (BER) requirement. With ever increasing data rate and lower BER requirement, meeting the timing margin, or limiting the timing jitter, becomes more and more critical. This tutorial will analyze the major jitter components in high speed links; explain how these jitter components are generated from circuitry and channel; demonstrate how the jitter components are measured in the lab; illustrate methods to reduce the jitter components; and finally review several system level clock architectures and analyze their jitter performance.