The Effect of Layout Design on Hot Carrier Degradation in N-type STI-LDMOS

In this work, the effect of gate length Lgand gate width Wgon hot carrier degradation (HCD) in shallow trench isolation n-type lateral double diffusion MOS (STI-NLDMOS) fabricated by 55 nm CMOS standard process is investigated. As Wgdecreases, the degradation of Ron,spin short-channel devices initially falls and then increase rapidly. TCAD simulations indicate that severe self-heating in wide-channel devices suppresses impact ionization rate. At the same time, hot hole injection becomes the dominant degradation mechanism, resulting in a reduction of Ron,spas the channel width increases. The results suggest that employing a wider device layout can mitigate HCD in short channel devices.