Field Polysilicon Gate-Optimized NIR-Enhanced SPAD With 11.92% PDP at 905 nm and 47.6% Fill Factor

This article presents a near-infrared (NIR)-enhanced silicon single-photon avalanche diode (SPAD) fabricated in standard 180-nm bipolar-CMOS-DMOS (BCD) technology. The key innovation is a deep p-type implant (DPI)/N $^{-}$ buried layer (NBL) depletion structure, which is strategically engineered to significantly boost the photon detection probability (PDP) in the NIR spectrum. To address the inherent challenge of dark noise, we introduce and validate a field-optimized guard ring (GR) technique employing a polysilicon gate connected to the anode, which effectively suppresses the electric field in the GR region and mitigates premature edge breakdown (PEB). The efficacy of this design is rigorously demonstrated through a comprehensive study across multiple devices, combining technology computer-aided design (TCAD) simulations with experimental measurements. After thorough optimization, the fabricated SPAD with a 20- $\boldsymbol {\mu }$ m active diameter (AD) achieves a peak PDP of 61.98% at 555 nm, a notably high NIR PDP of 11.92% at 905 nm, and a low dark count rate (DCR) of 2.2 cps/ $\boldsymbol {\mu }$ m² at 5-V excess bias, while maintaining a 42.5-V breakdown voltage and a 47.6% fill factor (FF). This work provides a validated and cost-effective solution for high-performance SPADs, making it ideally suited for 3-D sensing for consumer electronics, short-range fill-in light detection and ranging (LiDAR), and fluorescence lifetime imaging microscopy (FLIM).