Layout-Aware and Fabrication-Tolerant Deep Photonic Networks

We propose a systematic approach to design complex and universally capable deep photonic networks with inherent robustness to fabrication-induced variations. We first create a framework that incorporates layers of variation-aware, custom-designed Mach-Zehnder interferometers and virtual wafer maps to optimize integrated photonic devices under fabrication imperfections. Using this framework, we propose designs for silicon-based, broadband 50/50 splitters and 5% power taps demonstrating transmissions within ±2% and ±1.5% of their respective targets across the 1.5-1.6 μm spectrum, even in the presence of fabrication variations of ±15 nm in waveguide width and ±10 nm in thickness. Due to their consistent performance under fabrication-induced variations, we show that the potential fabrication yield for these tolerant devices is drastically higher than traditional devices. Our results underscore the effectiveness of the deep photonic network architecture in building layout-aware photonic systems, showcasing a realistic pathway towards creating inherently robust geometries with consistent performance for maximum yield and device reliability in future photonic applications.