Low-power, 4D (global) optical interconnects for wide word processing

The integration of photonic interconnects at the gate-to-gate level within the digital electronic environment has been demonstrably shown to significantly reduce the power consumption of the gate, and therefore, the circuit as well as the resulting system. This reduction can exceed two orders of magnitude when compared to current semiconductor implementations. Specifically, switching energies of 6 femto Joules (fJ) per bit have been achieved as compared to conventional implementations which range from several tens to several hundreds of fJ. Two fJ should be achievable with the correct balance of photonic and electronic technologies. HPOC modules with greater than 5,000,000 usable gates are projected to have sub-threshold leakage currents at < 10 nA and threshold currents of 1.25 (mu) A at a 1 GHz clock rate.