Recessed-Channel WSe2 Field-Effect Transistor via Self-Terminated Doping and Layer-by-Layer Etching

材料科学 兴奋剂 蚀刻(微加工) 光电子学 图层(电子) 场效应晶体管 频道(广播) 纳米技术 晶体管 电气工程 工程类 电压
作者
Dongryul Lee,Yongha Choi,Jung-Hun Kim,Jihyun Kim,Jihyun Kim,Jihyun Kim
出处
期刊:ACS Nano [American Chemical Society]
卷期号:16 (5): 8484-8492 被引量:31
标识
DOI:10.1021/acsnano.2c03402
摘要

Effective channel control with low contact resistance can be accomplished through selective ion implantation in Si and III-V semiconductor technologies; however, this approach cannot be adopted for ultrathin van der Waals materials. Herein, we demonstrate a self-aligned fabrication process based on self-terminated p-doping and layer-by-layer chemical etching to achieve low contact resistance as well as a high on/off current ratio in ultrathin tungsten diselenide (WSe2) field-effect transistors (FETs). Damage-free layer-by-layer thinning of the WSe2 channel is repeated up to a thickness of approximately 1.4 nm, while maintaining the selectively p-doped source/drain regions. The device characteristics of the recessed-channel WSe2 FET are systematically monitored during this layer-by-layer recess-channel process. The WSe2 etching rate is estimated to be 2-3 layers per cycle of oxidation and subsequent chemical etching. The self-terminated tungsten oxide (WOX) layer grown through ultraviolet-ozone treatment induces robust p-doping in the neighboring (or underlying) WSe2 through the electron withdrawal mechanism, which remains in the source/drain regions after channel oxide removal. The adopted self-terminated and self-aligned recess-channel process for ultrathin WSe2 FETs enables the realization of a high on/off output current ratio (>108) and field-effect mobility (∼190 cm2/V·s), while maintaining low contact resistance (0.9-6.1 kΩ·μm) without a postannealing process. The proposed facile and reproducible doping and atomic-layer-etching method for the fabrication of a recessed-channel FET with an ultrathin body can be helpful for high-performance two-dimensional semiconductor devices and is applicable to post-Si complementary metal-oxide semiconductor devices.
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