Improving FinFET Junctions and Contacts via Laser Annealing

Semiconductor industry transitions from the era of planar FETs to the era of three-dimensional (3D) transistors greatly improving performance per footprint. In planar FETs, the gate width W G , the lateral source/drain (S/D) size, and the metallic contact width W C are all equal to the transistor width W. FinFETs feature a 3D channel geometry where the gate perimeter W G per fin or, equivalently, the effective channel width W eff is significantly larger than the fin pitch P that defines the S/D and metallic contact width per fin (Fig. 1). Large W eff reduces the channel resistance but small P increases the parasitic external resistance R EXT making it a performance limiting factor. Innovative processes and new materials are required for reducing components of R EXT thereby realizing FinFET performance advantage. This work explores millisecond and nanosecond laser annealing techniques for reducing FinFET R EXT focusing on source/drain and contact resistances. Transistor-level specific contact resistivity in sub 10 ^-9 Ω-cm ² range has been achieved for both nFETs and pFETs with corresponding improvements in R EXT and switching currents.