Design Techniques for High-Speed and Low Power SAR ADC: A Review

Successive approximation registers (SAR) and analog-to-digital converters (ADCs) are energy efficient and suitable for fine CMOS process technology because they use comparators instead of ample power-consuming operational amplifiers. The speed of SAR ADC is constrained when using a binary search technique. Thus, there are fewer real-world uses for traditional SAR ADC. This paper has reviewed different design techniques for ultra-low power SAR ADC and high-speed SAR ADC. The most recent advancement demonstrates the wide range of applications for SAR-based ADC, from high-speed wireless/wired communication networks to low-speed biological sensors. This property of SAR-based ADC can be achieved with the help of hybrid SAR ADC design and innovative switching methodology for DAC of SAR ADC. This work presents a compelling overview of design methods for low-power and high-speed SAR ADC.