Design Flow for Reconfiguration Based on the Overlaying Concept

Reconfigurable hardware combines the flexibility of software and the efficiency of hardware. Thus, embedded systems can benefit from reconfiguration techniques. Many special aspects of dynamic and partial reconfiguration have been already analyzed. On the one hand reconfiguration is mostly used like a hot-plug mechanism. On the other hand approaches similar to the overlaying technique, known from the Pascal runtime library, can be used. The overlaying algorithm schedules different functions to the same hardware resource during runtime. In this paper, the overlaying concept is adapted to reconfiguration. The used reconfiguration model is presented and the costs are optimized and evaluated. The average reconfiguration time is minimized. These methods have been integrated into the design flow for reconfiguration. This approach is best suited for small FPGAs, which are crucial in embedded system design.