A 15-nA quiescent current capacitor-less LDO for sub-1V μW-powered fully-harvested systems

This work proposes a very-low quiescent current corner-compensated analog LDO with reconfigurable topology for multiple output voltage values, and its pW-powered voltage reference. The design of the proposed LDO has been optimized for sub-1V for battery-less systems that exhibit an average power consumption from hundreds nW up to hundreds of μW. Measurement results on a 180nm standard CMOS technology prove the effectiveness of the design strategy and validate the working principle of the LDO. The proposed analog LDO can work with a supply voltage down to 0.55-0.6V, consuming only 15-nA of quiescent current and it shows 6.4x lower FoMt (7.5x for FoMtv) compared with similar prior art.