Abnormal Negative Bias Stress Instability of Amorphous InGaZnO Thin Film Transistors

The negative bias stress normally yields a negative threshold voltage shift of the thin film transistors due to the additional positive charges trapped in the gate dielectrics or at channel/gate insulator interface. However, a positive threshold voltage shift of the device with the post InGaZnO deposition annealing at 400 o C is observed in our devices. The Na + incorporation from Mo gate into the gate dielectric after 400 o C annealing is responsible for this abnormal threshold voltage shift. The movement of Na + ions toward the gate electrode by the negative gate bias decreases the distance between the gate electrode and the Na + ions. Therefore, the voltage drop between the gate electrode and the Na + ions reduces, and a corresponding positive threshold voltage shift is observed. Inserting a SiN x layer between the SiO x gate insulator and the Mo gate electrode can reduce the Na + mobility, and thus a normal negative threshold voltage shift resumes. Experiment: A Mo layer with the thickness of 100 nm was sputtered on glass, and patterned as the gate electrode. Then 300 nm thick SiO x was deposited on the Mo gate electrode by plasma enhanced chemical vapor deposition (PECVD) at 350 o C. A 50 nm a-IGZO active layer was sputtered on SiO x . PDA was performed with an O 2 /N 2 gas with a mixing ratio of 1:4, and the annealing temperature is 350 o C or 400 o C for 1 hour. A 200 nm SiO x layer was deposited on the active layer by PECVD at 200 o C as the etch-stop layer. After that, 100 nm Mo was sputtered as the source and drain electrodes. The channel width and length of all TFTs are 20μm and 10μm, respectively. Additional 100 nm thick SiO x was deposited by PECVD at 200 o C as the passivation layer. Result and Discussion: The slightly negative V T shift of the device with 350 o C PDA after negative bias stress (NBS) was mainly attributed to the hole-trapping in the gate insulator [1] or at the a-IGZO/gate insulator interface [2]-[3]. As the trapped holes increase, the V T shifts to the negative direction. However, the abnormally negative V T shift of the device with 400 o C PDA after NBS was due to the motion of mobile Na + in the gate insulator [4]. The Mo electrode has the Na + concentration of ∼1×10 15 cm −3 , which was confirmed by second ion mass spectroscopy (SIMS). These results suggest that the origin of Na + may be due to the contamination or the purity of Mo target. On the other hand, the peak concentration of Na + in the device with 400 o C PDA is approximately 5X of 350 o C PDA. Fig. 1 shows the transfer characteristics of devices after NBS prebiased with a positive gate voltage (V GS =20V for 600 seconds). The larger positive V T shift of 400 o C PDA TFT with prebias after NBS than the fresh devices is due to the large movement of Na + toward gate electrode. Fig. 2(a) and (b) shows the band diagram to illustrate the Na + effect. During the prebias period, Na + near the SiO x /Mo gate electrode interface drifts toward the a-IGZO channel. When negative bias is applied at the Mo gate, Na + moves toward the gate electrode. As the distance between Na + and gate electrode decreases, the negative voltage drop at the gate electrode decreases, which “effectively” shifts the V T to the positive direction. In order to reduce the impact of Na + movement, a 50nm SiN x layer was inserted between the SiO x insulator and the Mo gate electrode, and the V T shift after NBS with prebias recovered to negative direction. For SIMS measurement, the peak concentration of Na + near SiO x and SiN x interface of the device with SiN x layer are smaller than near SiO x and Mo interface of the device without SiN x layer. On the other hand, the Na + trapped in SiNx has low mobility and relatively low movement during NBS [5]. Therefore, the effectively positive voltage shift caused by Na + movement is suppressed, and thus improves the reliability of 400 o C PDA device. Acknowledgement: The support of INNOLUX and the Ministry of Science and Technology, Taiwan (MOST 108-2622-8-002-016, MOST 108-2218-E-002-027) is highly acknowledged. [1] Y. K. Moon et al ., JJAP (2009) [2] E. N. Cho et al ., Trans. Device Mater. Rel. (2011) [3] W. T. Chen et al ., EDL (2011) [4] C. Lo et al ., J-EDS (2016) [5] B.-D. Choi et al ., JJAP (2005) Figure 1