Investigation of the Impact of Ferroelectricity Boosted Gate Stacks for 3D NAND on Short Time Data Retention and Endurance

Ferroelectricity boosted gate stacks, such as dual ferroelectric layer and charge trap layer (dual FE-CTL), have been proposed and confirmed to lead to improvements in program performance. However, the detailed analysis of reliability on the devices has not been sufficiently investigated to date. In this work, short time data retention and program/erase cycling endurance on dual FE-CTL gate stacks are investigated by fast 1-V. The results reveal significant advantages of dual FE-CTL gate stacks in memory reliability. In addition, lower transient gate current during program is observed, which is related to the improvements on dual FE-CTL gate stacks.