A 3.2-GHz Ring-Oscillator-Based Charge-Pump PLL With Time-Domain Optimization of PFD Reset Delay

This brief presents a time-domain method to optimize the phase-frequency detector (PFD) reset delay,$\tau _{reset}$, in charge-pump (CP) phase-locked loops (PLLs). In charge-pump PLLs (CP-PLLs), reducing$\tau _{reset}$generally lowers the reference spur and can improve jitter, but an excessively small$\tau _{reset}$causes the PFD dead-zone operation and degrades jitter. To narrow$\tau _{reset}$search space and identify its optimum, the proposed method uses a SystemVerilog (SV)-based PFD-CP behavioral model that represents current settling, charge sharing, charge injection, and clock feedthrough using piecewise exponential functions to reproduce the CP output-current waveform. Compared with a conventional phase-domain model, the proposed model predicts$\tau _{reset}$-dependent PLL behavior more accurately. At$\tau _{reset} = 100$ps, the jitter prediction error is reduced from 66.7% to 8.7%. In addition, the proposed reference-spur-based$\tau _{reset}$selection identifies the same optimum$\tau _{reset}$as the postlayout simulation. A 3.2-GHz prototype CP-PLL fabricated in 28-nm CMOS validates the proposed method and, at the optimized$\tau _{reset}$, achieves an rms jitter of 1.12 ps, a reference spur of −56.4 dBc, apower efficiency of 1.09 mW/GHz, and an FoM${}_{J}$of −233.6 dB.