A DTC-Assisted Radiation Tolerant Sub-Sampling Fractional-N Phase-Locked Loop

This paper presents a study on the radiation effects on a Fractional-N sub-sampling all-digital phase-locked loop (frac-N SS-ADPLL) and the associated hardening techniques implemented in a commercial 65 nm CMOS process. A digital-to-time converter (DTC)-assisted bang-bang phase detector (BBPD) is used to resolve fractional phase information which is shown to be inherently tolerating single-event effects (SEEs). An adaptive background calibration algorithm compensates for DTC gain errors induced by total ionizing dose (TID). The subsampling operation eliminates the need for a high-frequency divider, thereby avoiding the power overhead that triple modular redundancy (TMR) would impose, making this architecture advantageous in radiation environments. An experimental prototype was fabricated, and heavy-ion and laser testing confirm SEE resilience, while X-ray irradiation up to 100 Mrad results in a 3.9% resolution degradation and a 5.4% reduction in DTC power consumption. The proposed PLL achieves a frequency range of 2.35–2.83 GHz, a power consumption of 13.7 mW, and an integrated jitter of 2.32 ps. These results demonstrate a low-power, radiation-tolerant solution suitable for operation in harsh radiation environments.