材料科学
二硫化钼
晶体管
光电子学
电荷(物理)
电容器
蚀刻(微加工)
磁滞
图层(电子)
金属浇口
电压
纳米技术
电气工程
栅氧化层
凝聚态物理
物理
工程类
量子力学
冶金
作者
Po‐Cheng Tsai,Coung-Ru Yan,Shoou-Jinn Chang,Shu‐Wei Chang,Shih‐Yen Lin
出处
期刊:Nanotechnology
[IOP Publishing]
日期:2023-04-26
卷期号:34 (30): 305701-305701
被引量:4
标识
DOI:10.1088/1361-6528/acd064
摘要
Abstract We fabricate top-gate transistors on the three-layer molybdenum disulfide (MoS 2 ) with three, two, and one layers in the source and drain regions using atomic layer etching (ALE). In the presence of ALE, the device at zero gate voltage can exhibit high and low levels of drain current under the forward and reverse gate bias, respectively. The hysteresis loop on the transfer curve of transistor indicates that two distinct charge states exist in the device within a range of gate bias. A long retention time of the charge is observed. Unlike conventional semiconductor memories with transistors and capacitors, the two-dimensional (2D) material itself plays two parts in the current conduction and charge storage. The persistent charge storage and memory operation of the multilayer MoS 2 transistors with thicknesses of a few atomic layer will further expand the device application of 2D materials with reduced linewidths.
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