Improved HF-FOM and SC Ruggedness of Split-Gate 4H-SiC MOSFET With P+ Buffer

In this letter, a novel Split-Gate SiC MOSFET is proposed by introducing a P+ buffer (SG-PB-MOS) into the JFET region. The P+ buffer serves to enhance device oxide reliability by mitigating the peak oxide electric field ( E _max ). Besides, the P+ buffer facilitates depletion of the JFET region under high drain voltage, suppressing the short-circuit current. The SG-PB-MOS, Split-Gate MOSFET (SG-MOS), and conventional MOSFET (C-MOS) are sys-tematically characterized through TCAD simulations. Cell-level parameter distributions are observed and ana-lyzed to validate the efficacy of the proposed structure. In blocking states, the SG-PB-MOS demonstrates the mildest E _max . Moreover, compared to the C-MOS and SG-MOS, the SG-PB-MOS exhibits a 1.5× and 2.1× improvement in short-circuit withstand time (SCWT), a 5.2× and 2.4× im-provement in high-frequency figure-of-merit (HF-FOM, R _on × Q _gd ), respectively. Notably, these enhancements are achieved with negligible impact on R _on . As a result, SG-PB-MOSFET shows superior trade-offs in both R _on & E _max , R _on & SCWT, and R _on & Q _gd , making it suitable for high reliability and high power-density applications.