德拉姆
计算机科学
均衡器
电压
串行解串
延迟时间
电子工程
串扰
计算机硬件
电气工程
工程类
电信
频道(广播)
半导体存储器
内存控制器
作者
Seunghwan Hong,Chang-Hyun Bae,Yoo‐Chang Sung,Jaewoong Kim,Junsub Yoon,Sang‐Woo Kim,Jin-Hyeok Baek,Cheong-Ryong Cho,Useung Shin,Sang-Kyeom Kim,Hwan-Chul Jung,Hojun Chang,Janghoo Kim,Jeong-Sik Hwang,Hyunki Kim,Kiwon Lee,Dongmin Kim,Han-Ki Jeong,Myung-O Kim,Kyomin Sohn
标识
DOI:10.23919/vlsicircuits52068.2021.9492390
摘要
This paper presents a reflection and crosstalk canceling continuous-time linear equalizer (CTLE) for high-speed DDR SDRAM interface. To enhance the voltage margin in noisy multi-drop DDR SDRAM channel, the proposed CTLE cancels reflection noise by common-mode compensation and compensates crosstalk by limiting RC filter charging to overcome inversion of common-mode information. The reflection and crosstalk canceling CTLE is implemented in a DRAM process and improves the average voltage margin of 16GB RDIMM at 3.2Gbps with 28.3mV.
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